ok

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CHAPTER
14
Operational
Amplifiers
14.1 INTRODUCTION
An operational amplifier, or op-amp, is a very high gain differential amplifier with
high input impedance and low output impedance. Typical uses of the operational amplifier are to provide voltage amplitude changes (amplitude and polarity), oscillators,
filter circuits, and many types of instrumentation circuits. An op-amp contains a number of differential amplifier stages to achieve a very high voltage gain.
Figure 14.1 shows a basic op-amp with two inputs and one output as would result using a differential amplifier input stage. Recall from Chapter 12 that each input
results in either the same or an opposite polarity (or phase) output, depending on
whether the signal is applied to the plus ( ) or the minus ( ) input.
609
Input 1
Input 2
Output
–
+
Figure 14.1 Basic op-amp.
Single-Ended Input
Single-ended input operation results when the input signal is connected to one input
with the other input connected to ground. Figure 14.2 shows the signals connected
–
+
Vi
(a)
Vo
(b)
–
+
Vi
Vo
Figure 14.2 Single-ended operation.
for this operation. In Fig. 14.2a, the input is applied to the plus input (with minus input at ground), which results in an output having the same polarity as the applied input signal. Figure 14.2b shows an input signal applied to the minus input, the output
then being opposite in phase to the applied signal.
Double-Ended (Differential) Input
In addition to using only one input, it is possible to apply signals at each input—this
being a double-ended operation. Figure 14.3a shows an input,Vd, applied between
the two input terminals (recall that neither input is at ground), with the resulting amplified output in phase with that applied between the plus and minus inputs. Figure
14.3b shows the same action resulting when two separate signals are applied to the
inputs, the difference signal being Vi1 Vi2
.
610 Chapter 14 Operational Amplifiers
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Double-Ended Output
While the operation discussed so far had a single output, the op-amp can also be operated with opposite outputs, as shown in Fig. 14.4. An input applied to either input
will result in outputs from both output terminals, these outputs always being opposite in polarity. Figure 14.5 shows a single-ended input with a double-ended output.
As shown, the signal applied to the plus input results in two amplified outputs of opposite polarity. Figure 14.6 shows the same operation with a single output measured
–
+
(a)
Vo
(b)
–
+
Vo
Vd
V2
V1
Vd
Figure 14.3 Double-ended (differential) operation.
–
+
Vo
2
Vo
1
Vd
Vi –
+
Vo
2
Vo
1
–
+ Vi1
Vi2
Vo1
Vo2
Figure 14.4 Double-ended
output.
Figure 14.5 Double-ended output with single-ended input. Figure 14.6 Double-ended output.
between output terminals (not with respect to ground). This difference output signal
is Vo1 Vo2
. The difference output is also referred to as a floating signal since neither output terminal is the ground (reference) terminal. Notice that the difference output is twice as large as either Vo1
or Vo2
since they are of opposite polarity and subtracting them results in twice their amplitude [i.e., 10 V ( 10 V) 20 V]. Figure
14.7 shows a differential input, differential output operation. The input is applied between the two input terminals and the output taken from between the two output terminals. This is fully differential operation.
611 14.2 Differential and Common-Mode Operation
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+
Figure 14.7 Differential-input,
differential-output operation.
Common-Mode Operation
When the same input signals are applied to both inputs, common-mode operation results, as shown in Fig. 14.8. Ideally, the two inputs are equally amplified, and since
they result in opposite polarity signals at the output, these signals cancel, resulting in
0-V output. Practically, a small output signal will result.
Figure 14.8 Common-mode
operation.
Common-Mode Rejection
A significant feature of a differential connection is that the signals which are opposite at the inputs are highly amplified, while those which are common to the two inputs are only slightly amplified—the overall operation being to amplify the difference signal while rejecting the common signal at the two inputs. Since noise (any
unwanted input signal) is generally common to both inputs, the differential connection tends to provide attenuation of this unwanted input while providing an amplified
output of the difference signal applied to the inputs. This operating feature, referred
to as common-mode rejection, is discussed more fully in the next section.
14.2 DIFFERENTIAL AND COMMONMODE OPERATION
One of the more important features of a differential circuit connection, as provided
in an op-amp, is the circuit’s ability to greatly amplify signals that are opposite at the
two inputs, while only slightly amplifying signals that are common to both inputs. An
op-amp provides an output component that is due to the amplification of the difference of the signals applied to the plus and minus inputs and a component due to the
signals common to both inputs. Since amplification of the opposite input signals is
much greater than that of the common input signals, the circuit provides a commonmode rejection as described by a numerical value called the common-mode rejection
ratio (CMRR).
Differential Inputs
When separate inputs are applied to the op-amp, the resulting difference signal is the
difference between the two inputs.
Vd Vi1 Vi2
(14.1)
Common Inputs
When both input signals are the same, a common signal element due to the two inputs can be defined as the average of the sum of the two signals.
Vc 1
2
(Vi1 Vi2
) (14.2)
Output Voltage
Since any signals applied to an op-amp in general have both in-phase and out-ofphase components, the resulting output can be expressed as
Vo AdVd AcVc
(14.3)
where Vd difference voltage given by Eq. (14.1)
Vc common voltage given by Eq. (14.2)
Ad differential gain of the amplifier
Ac common-mode gain of the amplifier
Opposite Polarity Inputs
If opposite polarity inputs applied to an op-amp are ideally opposite signals, Vi1
Vi2 Vs, the resulting difference voltage is
Eq. (14.1):Vd Vi1 Vi2 Vs ( Vs
) 2Vs
while the resulting common voltage is
Eq. (14.2):Vc 1
2
(Vi1 Vi2
) 1
2
[Vs ( Vs
)] 0
so that the resulting output voltage is
Eq. (14.3):Vo AdVd AcVc Ad(2Vs
) 0 2 AdVs
This shows that when the inputs are an ideal opposite signal (no common element),
the output is the differential gain times twice the input signal applied to one of the
inputs.
Same Polarity Inputs
If the same polarity inputs are applied to an op-amp,Vi1 Vi2 Vs
, the resulting difference voltage is
Eq. (14.1):Vd Vi1 Vi2 Vs Vs 0
612 Chapter 14 Operational Amplifiers
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+
while the resulting common voltage is
Eq. (14.2): Vc 1
2
(Vi1 Vi2
) 1
2
(Vs Vs
) Vs
so that the resulting output voltage is
Eq. (14.3): Vo AdVd AcVc Ad
(0) AcVs AcVs
This shows that when the inputs are ideal in-phase signals (no difference signal), the
output is the common-mode gain times the input signal,Vs, which shows that only
common-mode operation occurs.
Common-Mode Rejection
The solutions above provide the relationships that can be used to measure Ad
and Ac
in op-amp circuits.
1.To measure Ad
:Set Vi1 Vi2 Vs 0.5 V, so that
Eq. (14.1): Vd (Vi1 Vi2
) (0.5 V ( 0.5 V) 1 V
and Eq. (14.2): Vc 1
2
(Vi1 Vi2
) 1
2
[0.5 V ( 0.5 V)] 0 V
Under these conditions the output voltage is
Eq. (14.3): Vo AdVd AcVc Ad
(1 V) Ac
(0) Ad
Thus, setting the input voltages Vi1 Vi2 0.5 V results in an output voltage
numerically equal to the value of Ad
.
2.To measure Ac
:Set Vi
1 Vi2 Vs 1 V, so that
Eq. (14.1): Vd (Vi1 Vi2
) (1 V 1 V) 0 V
and Eq. (14.2): Vc 1
2
(Vi1 Vi2
) 1
2
(1 V 1 V) 1 V
Under these conditions the output voltage is
Eq. (14.3): Vo AdVd AcVc Ad
(0 V) Ac
(1 V) Ac
Thus, setting the input voltages Vi1 Vi2 1 V results in an output voltage
numerically equal to the value of Ac
.
Common-Mode Rejection Ratio
Having obtained Ad
and Ac (as in the measurement procedure discussed above), we
can now calculate a value for the common-mode rejection ratio (CMRR), which is
defined by the following equation:
CMRR
A
A
d
c
(14.4)
The value of CMRR can also be expressed in logarithmic terms as
CMRR (log) 20 log10
A
A
d
c
(dB) (14.5)
613 14.2 Differential and Common-Mode Operation
−
+
Calculate the CMRR for the circuit measurements shown in Fig. 14.9.
614 Chapter 14 Operational Amplifiers
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+
Solution
From the measurement shown in Fig. 14.9a, using the procedure in step 1 above, we
obtain
Ad
V
V
o
d

1
8
m
V
V
8000
The measurement shown in Fig. 14.9b, using the procedure in step 2 above, gives us
Ac
V
V
o
c

1
1
2
m
m
V
V
12
Using Eq. (14.4), the value of CMRR is
CMRR
A
A
d
c

80
1
0
2
0
666.7
which can also be expressed as
CMRR 20 log10
A
A
d
c
20 log10666.7 56.48 dB
EXAMPLE 14.1
–
+
–
+
–
+
–
+
Vd
= 8 V
Vo
Vi2
= −0.5 mV
(a)
Vd
= 1 mV
Vo
= 8 V
Vi
1
= 1 mV
Vo
= 12 mV
Vc
= 1 mV
Vo
= 12 mV
(b)
Vi1
= 0.5 mV
Vi2
= 1 mV
Figure 14.9 Differential and common-mode operation: (a) differential-mode; (b)
common-mode.
It should be clear that the desired operation will have Ad
very large with Acvery
small. That is, the signal components of opposite polarity will appear greatly amplified at the output, whereas the signal components that are in phase will mostly cancel out so that the common-mode gain,Ac, is very small. Ideally, the value of the
CMRR is infinite. Practically, the larger the value of CMRR, the better the circuit operation.
We can express the output voltage in terms of the value of CMRR as follows:
Eq. (14.3): Vo AdVd AcVc AdVd

1
A
A
d
cV
V
c
d

Using Eq. (14.4), we can write the above as
Vo AdVd

1
CM
1
RR

V
V
d
c

(14.6)
Even when both Vd
and Vc
components of signal are present, Eq. (14.6) shows that
for large values of CMRR, the output voltage will be due mostly to the difference
signal, with the common-mode component greatly reduced or rejected. Some practical examples should help clarify this idea.
Determine the output voltage of an op-amp for input voltages of Vi1 150 V,Vi2
140 V. The amplifier has a differential gain of Ad 4000 and the value of CMRR
is:
(a) 100.
(b) 10
5
.
Solution
Eq. (14.1): Vd Vi1 Vi2 (150 140) V 10 V
Eq. (14.2): Vc
1
2
(Vi1 Vi2
)
150 V
2
140 V 145 V
(a) Eq. (14.6): Vo AdVd

1
CM
1
RR

V
V
d
c

(4000)(10 V)

1
1
1
00

1
1
4
0
5


V
V

40 mV(1.145) 45.8 mV
(b) Vo (4000)(10 V)

1
1
1
0
5
1
1
4
0
5


V
V

40 mV(1.000145) 40.006 mV
Example 14.2 shows that the larger the value of CMRR, the closer the output voltage is to the difference input times the difference gain with the common-mode signal being rejected.
14.3 OP-AMP BASICS
An operational amplifier is a very high gain amplifier having very high input impedance (typically a few megohms) and low output impedance (less than 100 ). The
basic circuit is made using a difference amplifier having two inputs (plus and minus)
and at least one output. Figure 14.10 shows a basic op-amp unit. As discussed ear-615 14.3 OP-AMP Basics
−
+
EXAMPLE 14.2
lier, the plus ( ) input produces an output that is in phase with the signal applied,
while an input to the minus ( ) input results in an opposite polarity output. The ac
equivalent circuit of the op-amp is shown in Fig. 14.11a. As shown, the input signal
applied between input terminals sees an input impedance,Ri, typically very high. The
output voltage is shown to be the amplifier gain times the input signal taken through
an output impedance,Ro, which is typically very low. An ideal op-amp circuit, as
shown in Fig. 14.11b, would have infinite input impedance, zero output impedance,
and an infinite voltage gain.
616 Chapter 14 Operational Amplifiers
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+
Basic Op-Amp
The basic circuit connection using an op-amp is shown in Fig. 14.12. The circuit
shown provides operation as a constant-gain multiplier. An input signal,V1, is applied
through resistor R1to the minus input. The output is then connected back to the same
minus input through resistor Rf
. The plus input is connected to ground. Since the signal V1 is essentially applied to the minus input, the resulting output is opposite in
phase to the input signal. Figure 14.13a shows the op-amp replaced by its ac equivalent circuit. If we use the ideal op-amp equivalent circuit, replacing Ri by an infinite
resistance and Ro
by zero resistance, the ac equivalent circuit is that shown in Fig.
14.13b. The circuit is then redrawn, as shown in Fig. 14.13c, from which circuit analysis is carried out.
Figure 14.10 Basic op-amp.
Figure 14.12 Basic op-amp connection.
Ri
Ro
AdVd
(a)
AdVd
(b)
Vd Vo Vd Vo
Figure 14.11 Ac equivalent of op-amp circuit: (a) practical; (b) ideal.
Using superposition, we can solve for the voltage V1in terms of the components
due to each of the sources. For source V1
only ( AvVi
set to zero),
Vi1
R1
R

f
Rf
V1
For source AvVi
only (V1
set to zero),
Vi2
R1
R

1
Rf
( AvVi
)
The total voltage Vi is then
Vi Vi1 Vi2
R1
R

f
Rf
V1
R1
R

1
Rf
( AvVi
)
which can be solved for Vi as
Vi
Rf (1
R

f
Av
)R1 V1
(14.7)
If Av 1 and AvR1 Rf, as is usually true, then
Vi
A
R
vR
f
1
V1
Solving for Vo
/Vi
,we get

V
V
o
i

A
V
v
i
Vi


V
A
i
v

A
R
v
fV
R
1
1

R
R
1
f

V
V
1
i

617 14.3 OP-AMP Basics
−
+
Figure 14.13 Operation of op-amp as constant-gain multiplier: (a) op-amp ac
equivalent circuit; (b) ideal op-amp equivalent circuit; (c) redrawn equivalent circuit.
so that
V
V
o
1

R
R
1
f
(14.8)
The result, in Eq. (14.8), shows that the ratio of overall output to input voltage is dependent only on the values of resistors R1
and Rf —provided that Av
is very large.
Unity Gain
If Rf R1, the gain is
voltage gain
R
R
1
f
1
so that the circuit provides a unity voltage gain with 180°phase inversion. If Rf
is exactly R1
, the voltage gain is exactly 1.
Constant Magnitude Gain
If Rf
is some multiple of R1
, the overall amplifier gain is a constant. For example, if
Rf 10R1, then
voltage gain
R
R
1
f
10
and the circuit provides a voltage gain of exactly 10 along with an 180°phase inversion from the input signal. If we select precise resistor values for Rf
and R1, we can
obtain a wide range of gains, the gain being as accurate as the resistors used and is
only slightly affected by temperature and other circuit factors.
Virtual Ground
The output voltage is limited by the supply voltage of, typically, a few volts. As stated
before, voltage gains are very high. If, for example,Vo 10 V and Av 20,000,
the input voltage would then be
Vi

A
V
v
o

2
1
0
0
,0
V
00
0.5 mV
If the circuit has an overall gain (Vo
/V1
) of, say, 1, the value of V1
would then be
10 V. Compared to all other input and output voltages, the value of Vi
is then small
and may be considered 0 V.
Note that although Vi 0 V, it is not exactly 0 V. (The output voltage is a few
volts due to the very small input Vi
times a very large gain Av
.) The fact that Vi
0 V leads to the concept that at the amplifier input there exists a virtual short circuit
or virtual ground.
The concept of a virtual short implies that although the voltage is nearly 0 V, there
is no current through the amplifier input to ground. Figure 14.14 depicts the virtual
ground concept. The heavy line is used to indicate that we may consider that a short
618 Chapter 14 Operational Amplifiers
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+
Figure 14.14 Virtual ground in
an op-amp.
exists with Vi 0 V but that this is a virtual short so that no current goes through the
short to ground. Current goes only through resistors R1
and Rf
as shown.
Using the virtual ground concept, we can write equations for the current Ias follows:
I
V
R
1
1

V
R
o
f

which can be solved for Vo
/V1
:

V
V
o
1

R
R
1
f

The virtual ground concept, which depends on Avbeing very large, allowed a simple
solution to determine the overall voltage gain. It should be understood that although
the circuit of Fig. 14.14 is not physically correct, it does allow an easy means for determining the overall voltage gain.
14.4 PRACTICAL OP-AMP CIRCUITS
The op-amp can be connected in a large number of circuits to provide various operating characteristics. In this section, we cover a few of the most common of these circuit connections.
Inverting Amplifier
The most widely used constant-gain amplifier circuit is the inverting amplifier, as
shown in Fig. 14.15. The output is obtained by multiplying the input by a fixed or
constant gain, set by the input resistor (R1
) and feedback resistor (Rf
)—this output
also being inverted from the input. Using Eq. (14.8) we can write
Vo
R
R
1
f
V1
619 14.4 Practical OP-AMP Circuits
−
+
If the circuit of Fig. 14.15 has R1 100 k and Rf 500 k , what output voltage
results for an input of V1 2 V?
Solution
Eq. (14.8):Vo
R
R
1
f
V1
5
1
0
0
0
0
k
k


(2 V) 10 V
EXAMPLE 14.3
–
Op-amp
+
V1
Rf
R1
V1 Vo − =
Rf
R1
Figure 14.15 Inverting constant-gain multiplier.
Noninverting Amplifier
The connection of Fig. 14.16a shows an op-amp circuit that works as a noninverting
amplifier or constant-gain multiplier. It should be noted that the inverting amplifier
connection is more widely used because it has better frequency stability (discussed
later). To determine the voltage gain of the circuit, we can use the equivalent representation shown in Fig. 14.16b. Note that the voltage across R1
is V1
since Vi 0 V.
This must be equal to the output voltage, through a voltage divider of R1
and Rf,so
that
V1
R1
R

1
Rf
Vo
which results in

V
V
o
1

R1
R

1
Rf
1
R
R
1
f
(14.9)
620 Chapter 14 Operational Amplifiers
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+
Calculate the output voltage of a noninverting amplifier (as in Fig. 14.16) for values
of V1 2 V,Rf 500 k , and R1 100 k .
Solution
Eq. (14.9):Vo

1
R
R
1
f

V1

1
5
1
0
0
0
0
k
k



(2 V) 6(2 V) 12 V
Unity Follower
The unity-follower circuit, as shown in Fig. 14.17a, provides a gain of unity (1) with
no polarity or phase reversal. From the equivalent circuit (see Fig. 14.17b) it is clear
that
Vo V1
(14.10)
and that the output is the same polarity and magnitude as the input. The circuit operates like an emitter- or source-follower circuit except that the gain is exactly unity.
EXAMPLE 14.4
Rf
–
Op-amp
V1
Rf
R1
( )V1 Vo + =
Rf
R1
1
(a)
Vi
≈ 0
V1
(b)
+
Vo R1
Figure 14.16 Noninverting constant-gain multiplier.
Summing Amplifier
Probably the most used of the op-amp circuits is the summing amplifier circuit shown
in Fig. 14.18a. The circuit shows a three-input summing amplifier circuit, which provides a means of algebraically summing (adding) three voltages, each multiplied by
a constant-gain factor. Using the equivalent representation shown in Fig. 14.18b, the
output voltage can be expressed in terms of the inputs as
Vo
R
R
1
f
V1
R
R
2
f
V2
R
R
3
f
V3

(14.11)
In other words, each input adds a voltage to the output multiplied by its separate constant-gain multiplier. If more inputs are used, they each add an additional component
to the output.
621 14.4 Practical OP-AMP Circuits
−
+
EXAMPLE 14.5
Figure 14.17 (a) Unity follower; (b) virtual-ground equivalent circuit.
Calculate the output voltage of an op-amp summing amplifier for the following sets
of voltages and resistors. Use Rf 1 M in all cases.
(a) V1 1 V,V2 2 V,V3 3 V,R1 500 k , R2 1 M , R3 1 M .
(b) V1 2 V,V2 3 V,V3 1 V,R1 200 k , R2 500 k , R3 1 M .
Figure 14.18 (a) Summing amplifier; (b) virtual-ground equivalent circuit.
Solution
Using Eq. (14.11):
(a) Vo
1
5
0
0
0
0
0
k
k


( 1 V)
1
1
0
0
0
0
0
0
k
k


( 2 V)
1
1
0
0
0
0
0
0
k
k


( 3 V)

[2(1 V) 1(2 V) 1(3 V)] 7 V
(b) Vo
1
2
0
0
0
0
0
k
k


( 2 V)
1
5
0
0
0
0
0
k
k


( 3 V)
1
1
0
0
0
0
0
0
k
k


( 1 V)

[5( 2 V) 2(3 V) 1(1 V)] 3 V
Integrator
So far, the input and feedback components have been resistors. If the feedback component used is a capacitor, as shown in Fig. 14.19a, the resulting connection is called
an integrator. The virtual-ground equivalent circuit (Fig. 14.19b) shows that an expression for the voltage between input and output can be derived in terms of the current I, from input to output. Recall that virtual ground means that we can consider
the voltage at the junction of Rand XCto be ground (since Vi 0 V) but that no current goes into ground at that point. The capacitive impedance can be expressed as
XC
j
1
C

s
1
C

622 Chapter 14 Operational Amplifiers
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+
where s j is in the Laplace notation.
*
Solving for Vo
/V1yields
I
V
R
1

X
V
C
o

1

/s
V
C
o
sCVo

V
V
o
1

s

C
1
R
(14.12)
The expression above can be rewritten in the time domain as
vo
(t)
R
1
C
v1
(t) dt (14.13)
*Laplace notation allows expressing differential or integral operations which are part of calculus in algebraic
form using the operator s. Readers unfamiliar with calculus should ignore the steps leading to Eq. (14.13) and
follow the physical meaning used thereafter.
Figure 14.19 Integrator.
Equation (14.13) shows that the output is the integral of the input, with an inversion and scale multiplier of 1/RC. The ability to integrate a given signal provides the
analog computer with the ability to solve differential equations and therefore provides
the ability to electrically solve analogs of physical system operation.
The integration operation is one of summation, summing the area under a waveform or curve over a period of time. If a fixed voltage is applied as input to an integrator circuit, Eq. (14.13) shows that the output voltage grows over a period of time,
providing a ramp voltage. Equation (14.13) can thus be understood to show that the
output voltage ramp (for a fixed input voltage) is opposite in polarity to the input voltage and is multiplied by the factor 1/RC. While the circuit of Fig. 14.19 can operate
on many varied types of input signals, the following examples will use only a fixed
input voltage, resulting in a ramp output voltage.
As an example, consider an input voltage,V1 1 V, to the integrator circuit of
Fig. 14.20a. The scale factor of 1/RCis

R
1
C

(1 M
1
)(1 F) 1
so that the output is a negative ramp voltage as shown in Fig. 14.20b. If the scale factor is changed by making R 100 k , for example, then

R
1
C

(100 k
1
)(1 F) 10
and the output is then a steeper ramp voltage, as shown in Fig. 14.20c.
623 14.4 Practical OP-AMP Circuits
−
+
Op-amp
+
–
(a)
R
(b)
υo
(t)
C = 1 F µ
(t) υ1 =1 V
−1 V
0 V
( )
RC
− =
1
1 −
RC
1 MΩ
0 V
−10 V
( ) − =
1
10 −
(c)
Figure 14.20 Operation of integrator with step input.
More than one input may be applied to an integrator, as shown in Fig. 14.21, with
the resulting operation given by
vo
(t)

R
1
1C
v1
(t) dt
R
1
2C
v2
(t) dt
R
1
3C
v3
(t) dt

(14.14)
An example of a summing integrator as used in an analog computer is given in
Fig. 14.21. The actual circuit is shown with input resistors and feedback capacitor,
whereas the analog-computer representation indicates only the scale factor for each
input.
Differentiator
A differentiator circuit is shown in Fig. 14.22. While not as useful as the circuit forms
covered above, the differentiator does provide a useful operation, the resulting relation for the circuit being
vo
(t) RC
dv
d
1
t
(t)
(14.15)
where the scale factor is RC.
624 Chapter 14 Operational Amplifiers
−
+
+
–
Vo
=200 kΩ R1
=100 kΩ R2
=1 MΩ R3
C = 1 F µ
(b)
V1
V2
V3
+
–
υo
(t)
(t) υ1
Op-amp
(t) υ2
(t) υ3
R1
R2
R3
C
(a)
V1
V2
V3
Vo
10
5
1
Op-amp
Figure 14.21 (a) Summing-integrator circuit; (b) component values; (c) analogcomputer, integrator-circuit representation.
Figure 14.22 Differentiator
circuit.
14.5 OP-AMP SPECIFICATIONS—DC
OFFSET PARAMETERS
Before going into various practical applications using op-amps, we should become
familiar with some of the parameters used to define the operation of the unit. These
specifications include both dc and transient or frequency operating features, as covered next.
Offset Currents and Voltages
While the op-amp output should be 0 V when the input is 0 V, in actual operation
there is some offset voltage at the output. For example, if one connected 0 V to both
op-amp inputs and then measured 26 mV(dc) at the output, this would represent
26 mV of unwanted voltage generated by the circuit and not by the input signal. Since
the user may connect the amplifier circuit for various gain and polarity operations,
however, the manufacturer specifies an input offset voltage for the op-amp. The output offset voltage is then determined by the input offset voltage and the gain of the
amplifier, as connected by the user.
The output offset voltage can be shown to be affected by two separate circuit conditions. These are: (1) an input offset voltage,VIO, and (2) an offset current due to
the difference in currents resulting at the plus ( ) and minus ( ) inputs.
INPUT OFFSET VOLTAGE, VIO
The manufacturer’s specification sheet provides a value of VIO for the op-amp. To
determine the effect of this input voltage on the output, consider the connection shown
in Fig. 14.23. Using Vo AVi, we can write
Vo AVi A

VIO Vo
R1
R

1
Rf

Solving for Vo
,we get
Vo VIO VIO
A[R1
/(R
A
1 Rf
)]
from which we can write
Vo
(offset) VIO
R1
R

1
Rf
(14.16)
Equation (14.16) shows how the output offset voltage results from a specified input
offset voltage for a typical amplifier connection of the op-amp.
A
1 A[R1
/(R1 Rf
)]
625 14.5 OP-AMP Specifications—DC Offset Parameters
−
+
+
–
Rf
Vi
Vo
Rf
VIO
R1
+ = 1
A
R1
VIO
RC
+
–
+
–
[ [ ( )
Figure 14.23 Operation showing
effect of input offset voltage, VIO
.
Calculate the output offset voltage of the circuit in Fig. 14.24. The op-amp spec lists
VIO 1.2 mV.
626 Chapter 14 Operational Amplifiers
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+
Solution
Eq. (14.16): Vo
(offset) VIO
R1
R

1
Rf
(1.2 mV)

2k
2

k
1

50 k
91.2 mV
OUTPUT OFFSET VOLTAGE DUE TO INPUT OFFSET CURRENT, IIO
An output offset voltage will also result due to any difference in dc bias currents at
both inputs. Since the two input transistors are never exactly matched, each will operate at a slightly different current. For a typical op-amp connection, such as that
shown in Fig. 14.25, an output offset voltage can be determined as follows. Replacing the bias currents through the input resistors by the voltage drop that each develops, as shown in Fig. 14.26, we can determine the expression for the resulting output voltage. Using superposition, the output voltage due to input bias current I

IB
,
denoted by V

o,is
V

o I

IB RC

1
R
R
1
f

while the output voltage due to only I

IB
, denoted by V

o,is
V

o I

IB R1


R
R
1
f


EXAMPLE 14.6
Figure 14.24 Op-amp connection for Examples 14.6 and 14.7.
Figure 14.25 Op-amp connection showing input bias currents. Figure 14.26 Redrawn circuit of Fig. 14.25.
for a total output offset voltage of
Vo
(offset due to I

IB
and I

IB
) I

IB RC

1
R
R
1
f

I

IB R1
R
R
1
f
(14.17)
Since the main consideration is the difference between the input bias currents rather
than each value, we define the offset current IIO by
IIO I

IB I

IB
Since the compensating resistance RCis usually approximately equal to the value of
R1
, using RC R1in Eq. (14.17) we can write
Vo
(offset) I

IB
(R1 Rf
) I

IB Rf
I

IBRf I

IB Rf Rf
(I

IB I

IB
)
resulting in
Vo
(offset due to IIO
) IIO Rf
(14.18)
Calculate the offset voltage for the circuit of Fig. 14.24 for op-amp specification listing IIO 100 nA.
Solution
Eq. (14.18): Vo IIO Rf (100 nA)(150 k ) 15 mV
TOTAL OFFSET DUE TO VIO
AND IIO
Since the op-amp output may have an output offset voltage due to both factors
covered above, the total output offset voltage can be expressed as
Vo
(offset) Vo
(offset due to VIO
) Vo
(offset due to IIO
) (14.19)
The absolute magnitude is used to accommodate the fact that the offset polarity may
be either positive or negative.
Calculate the total offset voltage for the circuit of Fig. 14.27 for an op-amp with specified values of input offset voltage, VIO 4 mV and input offset current IIO
150 nA.
627 14.5 OP-AMP Specifications—DC Offset Parameters
−
+
EXAMPLE 14.7
EXAMPLE 14.8
Figure 14.27 Op-amp circuit
for Example 14.8.
Solution
The offset due to VIO is
Eq. (14.16): Vo
(offset due to VIO
) VIO
R1
R

1
Rf
(4 mV)

5k
5

k
5

00 k
404 mV
Eq. (14.18): Vo
(offset due to IIO
) IIORf (150 nA)(500 k ) 75 mV
resulting in a total offset
Eq. (14.19): Vo
(total offset) Vo
(offset due to VIO
) Vo
(offset due to IIO
)
404 mV 75 mV 479 mV
INPUT BIAS CURRENT, IIB
A parameter related to IIO
and the separate input bias currents I

IB
and I

IB is the
average bias current defined as
IIB
I

IB
2
I

IB
(14.20)
One could determine the separate input bias currents using the specified values IIO
and IIB
. It can be shown that for I

IB
I

IB
I

IB IIB
I
2
IO
(14.21)
I

IB IIB
I
2
IO
(14.21)
Calculate the input bias currents at each input of an op-amp having specified values
of IIO 5 nA and IIB 30 nA.
Solution
Using Eq. (14.21):
I

IB IIB
I
2
IO
30 nA
5
2
nA
32.5 nA
I

IB IIB
I
2
IO
30 nA
5
2
nA
27.5 nA
14.6 OP-AMP SPECIFICATIONS—
FREQUENCY PARAMETERS
An op-amp is designed to be a high-gain, wide-bandwidth amplifier. This operation
tends to be unstable (oscillate) due to positive feedback (see Chapter 18). To ensure
stable operation, op-amps are built with internal compensation circuitry, which also
causes the very high open-loop gain to diminish with increasing frequency. This gain
reduction is referred to as roll-off. In most op-amps, roll-off occurs at a rate of 20 dB
628 Chapter 14 Operational Amplifiers
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+
EXAMPLE 14.9
per decade ( 20 dB/decade) or 6 dB per octave ( 6 dB/octave). (Refer to Chapter
11 for introductory coverage of dB and frequency response.)
Note that while op-amp specifications list an open-loop voltage gain (AVD), the
user typically connects the op-amp using feedback resistors to reduce the circuit voltage gain to a much smaller value (closed-loop voltage gain,ACL). A number of circuit improvements result from this gain reduction. First, the amplifier voltage gain is
a more stable, precise value set by the external resistors; second, the input impedance
of the circuit is increased over that of the op-amp alone; third, the circuit output impedance is reduced from that of the op-amp alone; and finally, the frequency response
of the circuit is increased over that of the op-amp alone.
Gain–Bandwidth
Because of the internal compensation circuitry included in an op-amp, the voltage
gain drops off as frequency increases. Op-amp specifications provide a description of
the gain versus bandwidth. Figure 14.28 provides a plot of gain versus frequency for
a typical op-amp. At low frequency down to dc operation the gain is that value listed
by the manufacturer’s specification AVD(voltage differential gain) and is typically a
very large value. As the frequency of the input signal increases the open-loop gain
drops off until it finally reaches the value of 1 (unity). The frequency at this gain value
is specified by the manufacturer as the unity-gain bandwidth, B1. While this value is
a frequency (see Fig. 14.28) at which the gain becomes 1, it can be considered a bandwidth, since the frequency band from 0 Hz to the unity-gain frequency is also a bandwidth. One could therefore refer to the point at which the gain reduces to 1 as the
unity-gain frequency (f1
) or unity-gain bandwidth (B1
).
629 14.6 OP-AMP Specifications—Frequency Parameters
−
+
Another frequency of interest is that shown in Fig. 14.28, at which the gain drops
by 3 dB (or to 0.707 the dc gain,AVD), this being the cutoff frequency of the op-amp,
fC. In fact, the unity-gain frequency and cutoff frequency are related by
f1 AVDfC (14.22)
Equation (14.22) shows that the unity-gain frequency may also be called the gain–
bandwidth product of the op-amp.
B1
Aυ
fC
0
0.707AVD
f
1
AVD
1 Frequency
(log scale)
Figure 14.28 Gain versus frequency plot.
Determine the cutoff frequency of an op-amp having specified values B1 1 MHz
and AVD 200 V/mV.
Solution
Since f1 B1 1 MHz, we can use Eq. (14.22) to calculate
fC
A
f
V
1
D

20
1
0
M
V
H
/m
z
V
2
1
00
10
1
6
0
3 5 Hz
Slew Rate, SR
Another parameter reflecting the op-amp’s ability to handling varying signals is slew
rate, defined as
slew rate maximum rate at which amplifier output can change in volts per
microsecond (V/ s)
SR
V
t
o
V/ s with t in s (14.23)
The slew rate provides a parameter specifying the maximum rate of change of the
output voltage when driven by a large step-input signal.
*
If one tried to drive the output at a rate of voltage change greater than the slew rate, the output would not be able
to change fast enough and would not vary over the full range expected, resulting in
signal clipping or distortion. In any case, the output would not be an amplified duplicate of the input signal if the op-amp slew rate is exceeded.
For an op-amp having a slew rate of SR 2 V/ s, what is the maximum closed-loop
voltage gain that can be used when the input signal varies by 0.5 V in 10 s?
Solution
Since Vo ACLVi, we can use

V
t
o
ACL
V
t
i

from which we get
ACL
V
V
o
i
/
/
t
t
V
S
i
R
/ t

0.5
2
V
V
/1
/
0
s
s 40
Any closed-loop voltage gain of magnitude greater than 40 would drive the output at
a rate greater than the slew rate allows, so the maximum closed-loop gain is 40.
*
The closed-loop gain is that obtained with the output connected back to the input in some way.
630 Chapter 14 Operational Amplifiers
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+
EXAMPLE 14.10
EXAMPLE 14.11
Maximum Signal Frequency
The maximum frequency that an op-amp may operate at depends on both the bandwidth (BW) and slew rate (SR) parameters of the op-amp. For a sinusoidal signal of
general form
vo Ksin(2
ft)
the maximum voltage rate of change can be shown to be
signal maximum rate of change 2
fK V/s
To prevent distortion at the output, the rate of change must also be less than the slew
rate, that is,
2
fK SR
K SR
so that f
2
SR
K
Hz

S
K
R
rad/s
(14.24)
Additionally, the maximum frequency,f, in Eq. (14.24), is also limited by the unitygain bandwidth.
For the signal and circuit of Fig. 14.29, determine the maximum frequency that may
be used. Op-amp slew rate is SR 0.5 V/ s.
631 14.6 OP-AMP Specifications—Frequency Parameters
−
+
Solution
For a gain of magnitude
ACL
R
R
1
f

2
1
4
0
0
k
k


24
the output voltage provides
K ACLVi 24(0.02 V) 0.48 V
Eq. (14.24):
S
K
R

0
0
.5
.4
V
8
/
V
s
1.1 10
6
rad/s
Since the signal’s frequency, 300 10
3
rad/s, is less than the maximum value
determined above, no output distortion will result.
EXAMPLE 14.12
Figure 14.29 Op-amp circuit
for Example 14.12.
14.7 OP-AMP UNIT SPECIFICATIONS
In this section, we discuss how the manufacturer’s specifications are read for a typical op-amp unit. A popular bipolar op-amp IC is the 741 described by the information provided in Fig. 14.30. The op-amp is available in a number of packages, an
8-pin DIP and a 10-pin flatpack being among the more usual forms.
632 Chapter 14 Operational Amplifiers
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+
Figure 14.30 741 op-amp specifications.
Absolute Maximum Ratings
The absolute maximum ratings provide information on what largest voltage supplies
may be used, how large the input signal swing may be, and at how much power the
device is capable of operating. Depending on the particular version of 741 used, the
largest supply voltage is a dual supply of 18 V or 22 V. In addition, the IC can
internally dissipate from 310 to 570 mW, depending on the IC package used. Table
14.1 summarizes some typical values to use in examples and problems.
633 14.7 OP-AMP Unit Specifications
−
+
Determine the current draw from a dual power supply of 12 V if the IC dissipates
500 mW.
EXAMPLE 14.13
Figure 14.30 Continued.
TABLE 14.1Absolute Maximum Ratings
Supply voltage 22 V
Internal power dissipation 500 mW
Differential input voltage 30 V
Input voltage 15 V
Solution
If we assume that each supply provides half the total power to the IC, then
P VI
250 mW 12 V(I)
so that each supply must provide a current of
I
25
1
0
2
m
V
W
20.83 mA
Electrical Characteristics
Electrical characteristics include many of the parameters covered earlier in this chapter. The manufacturer provides some combination of typical, minimum, or maximum
values for various parameters as deemed most useful to the user. A summary is provided in Table 14.2.
634 Chapter 14 Operational Amplifiers
−
+
VIO
Input offset voltage: The input offset voltage is seen to be typically
1 mV, but can go as high as 6 mV. The output offset voltage is then computed based
on the circuit used. If the worst condition possible is of interest, the maximum value
should be used. Typical values are those more commonly expected when using the
op-amp.
IIO
Input offset current: The input offset current is listed to be typically
20 nA, while the largest value expected is 200 nA.
IIB
Input bias current: The input bias current is typically 80 nA and may be
as large as 500 nA.
VICR
Common-mode input voltage range: This parameter lists the range that
the input voltage may vary over (using a supply of 15 V), about 12 to 13 V. Inputs larger in amplitude than this value will probably result in output distortion and
should be avoided.
VOM Maximum peak output voltage swing: This parameter lists the largest
value the output may vary (using a 15-V supply). Depending on the circuit closedTABLE 14.2 A741 Electrical Characteristics: VCC 15 V, TA 25°C
Characteristic MIN TYP MAX Unit
VIO Input offset voltage 1 6 mV
IIO Input offset current 20 200 nA
IIB Input bias current 80 500 nA
VICR Common-mode input voltage range 12 13 V
VOMMaximum peak output voltage swing 12 14 V
AVDLarge-signal differential voltage amplification 20 200 V/mV
ri Input resistance 0.3 2 M
roOutput resistance 75
Ci Input capacitance 1.4 pF
CMRR Common-mode rejection ratio 70 90 dB
ICCSupply current 1.7 2.8 mA
PDTotal power dissipation 50 85 mW
loop gain, the input signal should be limited to keep the output from varying by an
amount no larger than 12 V, in the worst case, or by 14 V, typically.
AVD Large-signal differential voltage amplification: This is the open-loop
voltage gain of the op-amp. While a minimum value of 20 V/mV or 20,000 V/V is
listed, the manufacturer also lists a typical value of 200 V/mV or 200,000 V/V.
ri
Input resistance: The input resistance of the op-amp when measured under open-loop is typically 2 M but could be as little as 0.3 M or 300 k . In a
closed-loop circuit, this input impedance can be much larger, as discussed previously.
ro
Output resistance: The op-amp output resistance is listed as typically 75 .
No minimum or maximum value is given by the manufacturer for this op-amp. Again,
in a closed-loop circuit, the output impedance can be lower, depending on the circuit
gain.
Ci
Input capacitance: For high-frequency considerations, it is helpful to know
that the input to the op-amp has typically 1.4 pF of capacitance, a generally small
value compared even to stray wiring.
CMRR Common-mode rejection ratio: The op-amp parameter is seen to be
typically 90 dB but could go as low as 70 dB. Since 90 dB is equivalent to 31622.78,
the op-amp amplifies noise (common inputs) by over 30,000 times less than difference inputs.
ICC Supply current: The op-amp draws a total of 2.8 mA, typically from the
dual voltage supply, but the current drawn could be as little as 1.7 mA. This parameter helps the user determine the size of the voltage supply to use. It also can be used
to calculate the power dissipated by the IC (PD 2VCCICC).
PD Total power dissipation: The total power dissipated by the op-amp is typically 50 mW but could go as high as 85 mW. Referring to the previous parameter,
the op-amp will dissipate about 50 mW when drawing about 1.7 mA using a dual
15-V supply. At smaller supply voltages, the current drawn will be less and the total
power dissipated will also be less.
Using the specifications listed in Table 14.2, calculate the typical output offset voltage for the circuit connection of Fig. 14.31.
635 14.7 OP-AMP Unit Specifications
−
+
EXAMPLE 14.14
Solution
The output offset due to VIO is calculated to be
Eq. (14.16): Vo
(offset) VIO
R1
R

1
Rf
(1 mV)

12 k
12

k
3

60 k
31 mV
The output voltage due to IIO is calculated to be
Figure 14.31 Op-amp circuit
for Examples 14.14, 14.15, and
14.17.
Eq. (14.18): Vo
(offset) IIORf 20 nA(360 k ) 7.2 mV
Assuming that these two offsets are the same polarity at the output, the total output
offset voltage is then
Vo
(offset) 31 mV 7.2 mV 38.2 mV
For the typical characteristics of the 741 op-amp (ro 75 , A 200 k ), calculate
the following values for the circuit of Fig. 14.31.
(a) ACL.
(b) Zi
.
(c) Zo
.
Solution
(a) Eq. (14.8):
V
V
o
i

R
R
1
f

3
1
6
2
0
k
k

30


1

(b) Zi R1 12 k
(c) Zo
(1
ro
A)
0.011
Operating Characteristics
Another group of values used to describe the operation of the op-amp over varying
signals are provided in Table 14.3.
75
1


3
1
0

(200 k )
636 Chapter 14 Operational Amplifiers
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+
Calculate the cutoff frequency of an op-amp having characteristics given in Tables
14.2 and 14.3.
Solution
Eq. (14.22):fC
A
f
V
1
D

A
B
V
1
D

1
20
M
,0
H
00
z
50 Hz
Calculate the maximum frequency of the input signal for the circuit in Fig. 14.31,
with an input of Vi 25 mV.
Solution
For a closed-loop gain of ACL 30 and an input of Vi 25 mV, the output gain factor is calculated to be
K ACLVi 30(25 mV) 750 mV 0.750 V
EXAMPLE 14.15
EXAMPLE 14.16
EXAMPLE 14.17
TABLE 14.3Operating Characteristics: VCC 15 V, TA 25°C
Parameter MIN TYP MAX Unit
B1Unity gain bandwidth 1 MHz
t
r Rise time 0.3 s
Using Eq. (14.24), the maximum signal frequency,fmax,is
fmax
2
SR
K

2
0
(
.5
0.7
V
5
/
0
s
V) 106 kHz
Op-Amp Performance
The manufacturer provides a number of graphical descriptions to describe the performance of the op-amp. Figure 14.32 includes some typical performance curves comparing various characteristics as a function of supply voltage. The open-loop voltage
gain is seen to get larger with a larger supply voltage value. While the previous
tabular information provided information at a particular supply voltage, the performance curve shows how the voltage gain is affected by using a range of supply
voltage values.
637 14.7 OP-AMP Unit Specifications
−
+
EXAMPLE 14.18 Using Fig. 14.32, determine the open-loop voltage gain for a supply voltage of
VCC 12 V.
Solution
From the curve in Fig. 14.32,AVD 104 dB. This is a linear voltage gain of
AVD(dB) 20 log10AVD
104 dB 20 log AVD
AVD antilog
1
2
0
0
4
158.5 10
3
Another performance curve in Fig. 14.32 shows how power consumption varies
as a function of supply voltage. As shown, the power consumption increases with
larger values of supply voltage. For example, while the power dissipation is about
50 mW at VCC 15 V, it drops to about 5 mW with VCC 5 V. Two other curves
show how the input and output resistances are affected by frequency, the input impedance dropping and the output resistance increasing at higher frequency.
Voltage gain (dB)
110 100
95
90
85
4 8 12 16
Power consumption (mW)
Supply voltage (+VCC)
80
60
40
20
0
10 15
20
Input resistance (Ω)
10 M
1 M 100 k 10 k 1 k
10 k
1 M
Output resistance (Ω)
100
Frequency (Hz)
100
100 k
1 M
100
Supply voltage (+VCC)
Frequency (Hz)
105
200
300
400
500
600
100 k 10 k 1 k 100 Figure 14.32 Performance
curves.
14.8 PSPICE WINDOWS
The evaluation version of PSpice has only four op-amp units. These are defined by
the subcircuit made up of various transistors, resistors, capacitors, and so on. These
are models of four of the more common op-amp units and have their unit specifications. One can model an op-amp to provide a more ideal unit—this being helpful
when describing theoretical circuit connections. Lets start by describing an op-amp
model that can be used to analyze circuits.
PSpice Op-Amp Model
An op-amp can be described by a schematic circuit having an input impedance,Ri
,
an output impedance,RO, and a voltage gain, Av
. Figure 14.33 shows this basic circuit, using the typical values of a 741 op-amp:
Ri 2 M , RO 75 , Av 200,000 200 V/mV
638 Chapter 14 Operational Amplifiers
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+
The values of input and output resistance are provided by resistor components with desired values. The gain of the op-amp is provided using a voltage-controlled voltage
source, schematic device part labeled E.Figure 14.34 shows setting the E device for a
gain of 200,000 (the device parameter GAINis set to a value of 200,000). The schematic
circuit of Fig. 14.33 thus represents a 741 op-amp with typical specs listed above.
Figure 14.33 PSpice ideal opamp model.
Figure 14.34 Setting gain of
part E.
Program 14.1—Inverting Op-Amp
An inverting op-amp of the type described in Example 14.3 and shown in Fig. 14.15
is considered first. Using the ideal model of Fig. 14.33, an inverting op-amp circuit
is drawn as in Fig. 14.35. With the dc voltage display turned on, the result after running an analysis shows that for an input of 2 V and a circuit gain of 5.
Av RF/R1 500 k /100 k 5
639 14.8 PSpice Windows
−
+
Figure 14.35 Inverting op-amp using ideal model.
The output is exactly 10 V
VO AvVi 5(2 V) 10 V
The input to the minus terminal is 50.01 V, which is virtually ground or 0 V.
A practical inverting op-amp circuit is drawn in Fig. 14.36. Using the same resistor
values as in Fig. 14.35 with a practical op-amp unit, the A741, the resulting output
is 9.96 V, near the ideal value of 10 V. This slight difference from the ideal is due
to the actual gain and input impedance of the A741 op-amp unit. Fig. 14.36 shows
dc voltages because the Enable Bias Voltage Displaywas set on. Notice the minus
input is 69.26 V for this op-amp circuit—slightly different from that using the opamp model of Fig. 14.33.
Figure 14.36 Practical inverting op-amp circuit.
An output listing from the analysis of Fig. 14.36 is shown in Fig. 14.37. Before
the analysis is done, selecting Analysis Setup, Transfer Function,and then Output
of V(RF:2)and Input Sourceof Vi will provide the small-signal characteristics in
the output listing. The circuit gain is seen to be
Figure 14.37 PSpice output for
inverting op-amp (edited).
VO/Vi 5
Input resistance at Vi 1 10
5
Output resistance at VO 4.95 10
3
Program 14.2—Noninverting Op-Amp
Fig. 14.38 shows a noninverting op-amp circuit. The bias voltages are displayed on
the figure. The theoretical gain of the amplifier circuit should be
Av (1 RF/R1) 1 500 k /100 k 6
640 Chapter 14 Operational Amplifiers
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+
For an input of 2 V, the resulting output will be
VO AvVi 5(2 V) 10 V
The output is noninverted from the input.
Program 14.3—Summing Op-Amp Circuit
A summing op-amp circuit such as that in Example 14.5 is shown in Fig. 14.39. Bias
voltages also are displayed in Fig. 14.39, showing the resulting output at 3 V, as was
Figure 14.38 Design Center
schematic for noninverting opamp circuit.
Figure 14.39 Summing amplifier for Program 14.3.
calculated in Example 14.5. Notice how well the virtual ground concept works with
the minus input being only 3.791 V.
Program 14.4—Unity-Gain Op-Amp Circuit
Figure 14.40 shows a unity-gain op-amp circuit with bias voltages displayed. For an
input of 2 V, the output is exactly 2 V.
641 14.8 PSpice Windows
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+
Program 14.5—Op-Amp Integrator Circuit
An op-amp integrator circuit is shown in Fig. 14.41. The input is selected as VPULSE,
which is set to be a step input as follows:
Set ac 0,dc 0,V1 0 V,V2 2 V,TD 0,TR 0,TF 0,PW 10 ms,
and PER 20 ms. This provides a step from 0 to 2 V, with no time delay, rise time
or fall time, having a period of 10 ms and repeating after a period of 20 ms. For this
problem, the voltage rises instantly to 2 V, then stays there for a sufficiently long time
for the output to drop as a ramp voltage from the maximum supply level of 20 V
to the lowest level of 20 V. Theoretically, the output for the circuit of Fig. 14.41 is
vO(t) 1/RC vi
(t) dt
vO(t) 1/(10 k )(0.01 F) 2 dt 10,000 2 dt 20,000t
Figure 14.40 Unity-gain amplifier.
Figure 14.41 Op-amp integrator circuit.
This is a negative ramp voltage dropping at a rate (slope) of 20,000 V/s. This ramp
voltage will drop from 20 V to 20 V in
40 V/20,000 2 10
3
2 ms
Fig. 14.42 shows the input step waveform and the resulting output ramp waveform
obtained using PROBE.
642 Chapter 14 Operational Amplifiers
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+
Program 14.6—Multistage Op-Amp Circuit
A multistage op-amp circuit is shown in Fig. 14.43. The input to stage 1 of 200 mV
provides an output of 200 mV to stages 2 and 3. Stage 2 is an inverting amplifier with
Figure 14.42 Probe waveform for integrator circuit.
Figure 14.43 Multistage op-amp circuit.
gain 200 k /20 k 10, with an output from stage 2 of 10(200 mV)
2 V. State 3 is a non-inverting amplifier with gain of (1 200 k /10 k 21), resulting in an output of 21(200 mV) 4.2 V.
§ 14.2 Differential and Common-Mode Operation
1.Calculate the CMRR (in dB) for the circuit measurements of Vd 1 mV,Vo 120 mV, and
VC 1 mV,Vo 20 V.
2.Determine the output voltage of an op-amp for input voltages of Vi
1 200 V and Vi
2 140
V. The amplifier has a differential gain of Ad 6000 and the value of CMRR is:
(a) 200.
(b) 10
5
.
§ 14.4 Practical Op-Amp Circuits
3.What is the output voltage in the circuit of Fig. 14.44?
643 Problems
−
+
PROBLEMS
Figure 14.44 Problems 3 and 25
Figure 14.45 Problem 4
4.What is the range of the voltage-gain adjustment in the circuit of Fig. 14.45?
5.What input voltage results in an output of 2 V in the circuit of Fig. 14.46?
644 Chapter 14 Operational Amplifiers
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+
6.What is the range of the output voltage in the circuit of Fig. 14.47 if the input can vary from
0.1 to 0.5 V?
7.What output voltage results in the circuit of Fig. 14.48 for an input of V1 0.3 V?
8.What input must be applied to the input of Fig. 14.48 to result in an output of 2.4 V?
9.What range of output voltage is developed in the circuit of Fig. 14.49?
10.Calculate the output voltage developed by the circuit of Fig. 14.50 for Rf 330 k .
11.Calculate the output voltage of the circuit in Fig. 14.50 for Rf 68 k .
+
–
Vo
20 kΩ
200 kΩ
V1
(0.1 to 0.5 V)
+
Vo
V1
360 kΩ
12 kΩ
–
+
–
Vo
200 kΩ
10 kΩ
10 kΩ
V1=0.5 V
+
–
Vo
Rf
33 kΩ
22 kΩ
12 kΩ
= +0.2 V V1
= –0.5 V V2
= +0.8 V V3
Figure 14.49 Problem 9 Figure 14.50 Problems 10, 11, and 27
Figure 14.46 Problem 5
Figure 14.47 Problem 6 Figure 14.48 Problems 7, 8, and 26
12.Sketch the output waveform resulting in Fig. 14.51.
13.What output voltage results in the circuit of Fig. 14.52 for V1 0.5 V?
645 Problems
−
+
+
–
Vo
200 kΩ
0.1 F µ
= +1.5 V V1
+
–
Vo
V1
Figure 14.51 Problem 12 Figure 14.52 Problem 13
14.Calculate the output voltage for the circuit of Fig. 14.53.
15.Calculate the output voltages V2
and V3
in the circuit of Fig. 14.54.
Figure 14.53 Problems 14 and 28
Figure 14.54 Problem 15
16.Calculate the output voltage,Vo
, in the circuit of Fig. 14.55.
646 Chapter 14 Operational Amplifiers
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+
17.Calculate Vo
in the circuit of Fig. 14.56.
§ 14.5 Op-Amp Specifications—DC Offset Parameters
*
18.Calculate the total offset voltage for the circuit of Fig. 14.57 for an op-amp with specified values of input offset voltage VIO 6 mV and input offset current IIO 120 nA.
Figure 14.55 Problems 16 and 29
Figure 14.56 Problem 17
*
19.Calculate the input bias current at each input of an op-amp having specified values of IIO
4 nA and IIB 20 nA.
§ 14.6 Op-Amp Specifications—Frequency Parameters
20.Determine the cutoff frequency of an op-amp having specified values B1 800 kHz and AVD
150 V/mV.
*
21.For an op-amp having a slew rate of SR 2.4 V/ s, what is the maximum closed-loop voltage gain that can be used when the input signal varies by 0.3 V in 10 s?
*
22.For an input of V1 50 mV in the circuit of Fig. 14.57, determine the maximum frequency
that may be used. The op-amp slew rate SR 0.4 V/ s.
23.Using the specifications listed in Table 14.2, calculate the typical offset voltage for the circuit
connection of Fig. 14.57.
*
24.For the typical characteristics of the 741 op-amp, calculate the following values for the circuit
of Fig. 14.57.
(a) ACL.
(b) Zi
.
(c) Zo
.
§ 14.8 PSpice Windows
*
25.Use Schematic Capture to draw a circuit to determine the output voltage in the circuit of Fig.
14.44.
*
26.Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.48 for the input
of Vi 0.5 V.
*
27.Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.50 for Rf
68 k .
*
28.Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.53.
*
29.Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.55.
*
30.Use Schematic Capture to calculate the output voltage in the circuit of Fig. 14.56.
*
31.Use Schematic Capture to obtain the output waveform for a 2 V step input to an integrator circuit, as shown in Fig. 14.20, with values of R 40 k and C 0.003 F.
*
Please Note: Asterisks indicate more difficult problems